Recently, a new write mechanism, which is based upon spin polarization current induced magnetization switching, has been introduced to the magnetic random access memory (MRAM) design. This new MRAM design, called Spin-Transfer Torque MRAM (STT-MRAM), uses a bidirectional writing current through the magnetic tunneling junction (MTJ) to realize the resistance switching. Depending on the direction of the writing current, the free ferromagnetic layer in the MTJ can be aligned parallel or anti-parallel to the pinned layer and consequently provide a different resistance state.
Each STT-MRAM memory cell usually includes one n-channel metal oxide semiconductor (NMOS) transistor to act as a switch (i.e. a select transistor) for selecting the cell during reading or writing. However, as STT-MRAM memory cells scales down with complementary metal oxide semiconductor (CMOS) technology, the driving ability (in opposing current flows) across the STT-MRAM becomes more asymmetric. The transition between the 2 states occurs beyond a threshold current or voltage applied to the MTJ. The required threshold current dictates the size of the word-line select transistor and limits the extent in which STT-MRAM memory cells can be scaled down. The current flow is further exacerbated in the direction from select transistor to the MTJ. FIG. 1A is a schematic 100a showing a current flowing though select transistor 102 and MTJ 104 in a first direction, i.e. from the MTJ 104 to the select transistor 102. FIG. 1B is a schematic 100b showing a current flowing though select transistor 102 and MTJ 104 in a first direction, i.e. from the select transistor 102 to the MTJ 104. As shown in FIGS. 1A and 1B, the current flow in the direction from the select transistor 102 to the MTJ 104 is constricted as the potential drop across MTJ 104 reduces the available gate drive across transistor 102. Consequently, the gate drive across transistor 102 is less than VDD. Negative feedback due to source degeneration worsens the situation. The problems are not limited to only write operations. These issues require the n-channel metal oxide semiconductor (NMOS) transistor 102 of the STT-MRAM memory cell to maintain a relatively large area which limits the ability to scale down the technology.
The usage of a transmission gate in place of the NMOS has been proposed by prior-arts to circumvent the issue. However, the transmission gate has limited functionality and serves solely as a word-line selection switch. The terminal of the transmission gate that is not connected to the MTJ is known commonly as the source line (SL). The terminal of the MTJ that is not connected to the transmission gate is known commonly as the bit line (BL). FIG. 1C is a schematic illustrating a memory array. A STT-MRAM memory cell 152 of the memory array includes a transmission gate 154 and a MTJ 156. The transmission gate 154 is coupled by source line (SL) 158 to source line (SL) driver 160. The MTJ 156 is coupled by bit line (BL) 162 to bit line (BL) driver 164. Both the source line 158 and bit line 162 has to be driven by drivers 160, 164 external to the memory cell 152 and array. It other words, having both the SL and BL lines 158, 162 inevitably necessitates a two port access (i.e. via both SL 158 and BL 162) to an individual memory cell 152. The task of decoding of both the SL line 156 and BL line 158 is the burden of the column decoder. Further, high RC capacitance may exist on the SL line 158 and BL line 162.